1. Field of the Invention
The present invention relates to an output circuit in a semiconductor device including a logic circuit and/or a memory circuit, and in particular to a structure of an output circuit which is arranged at an output stage of a semiconductor integrated circuit chip, for fast and stable transmission of signals.
2. Description of the Background Art
With increase in operation speed of semiconductor integrated circuits, speeds of signal transmission between a plurality of integrated circuit devices have been increased. For fast transmission, it is necessary to reduce transition times (i.e., rising time and falling time) of a signal to be transmitted. If the signal amplitude is large, the issues in connection with crosstalk noises caused by capacitive coupling between signal lines, switching noises causing ringing of signals, electromagnetic radiation resulting from fast charging and discharging of signal lines and increase in power consumption become more significant. For overcoming these problems, various methods for transmitting signals with reduced signal amplitude have been proposed or developed, and such a method has been known that a terminating resistance is arranged at a signal input side for reducing the signal amplitude by this terminating resistance. As one of the methods for reducing the signal amplitude in the above manner, the class I method in SSTL-3 (Stub Series Terminated Logic for 3.3 V) has been proposed.
Also, Japanese Patent Laying-Open No. 6-326591 (1994) has disclosed an amplitude limiting circuit of such type.
In the structure wherein the signal amplitude is limited by such a terminating resistance, a signal level depends on a resistance ratio between a resistance (on-resistance) of a transistor (MOS transistor) in the on state included in an output circuit and a terminating resistance. However, a DC current flows from the terminating resistance through a transmission path to the transistor in the on state of the output circuit, which increases the current consumption.
The resistance value of the terminating resistance depends on the value of the intrinsic impedance of the transmission line (because the impedance matching is established to prevent waveform distortion due to reflection of signals). Therefore, when the signal amplitude is determined, the resistance value of this terminating resistance is determined in advance, so that the on-resistance of the transistor at the final output stage of this output circuit is uniquely determined for achieving the required amplitude limitation. In an unsaturated region, a ratio between a drain current of a MOS transistor and a voltage between a drain and a source, i.e., a drain-source voltage is given as a function of a ratio .beta. between the channel width and the channel length. When the on-resistance is determined, therefore, the value of this coefficient or ratio .beta. is determined, so that a current drive capability of this output MOS transistor is determined in advance. Therefore, a fan-out at the output circuit is limited, and fast driving of a large number of circuits becomes difficult.
For overcoming the problems in the structure which uses the terminating resistance for achieving the small amplitude operation, such a structure has been proposed that the operation power supply voltage level of the output circuit is adjusted, so that the output circuit itself adjusts the output signal amplitude (see Japanese Patent Laying-Open No. 6-326591 (1994)).
FIG. 65 shows a structure of an output portion of a semiconductor integrated circuit device in the prior art, which is disclosed, e.g., in the foregoing prior art reference.
In FIG. 65, a conventional semiconductor integrated circuit device CH includes a power supply circuit PW1 which produces an internal power supply voltage VCC1 lower than a power supply voltage VCC in accordance with an internally generated reference voltage VTT, a power supply circuit PW2 which produces another internal power supply voltage VSS1 higher than a ground voltage VSS in accordance with reference voltage VTT, and an output circuit OB which operates using, as operation power supply voltages, both of internal power supply voltage VCC1 on internal power supply line CL and power supply voltage VSS1 on internal ground line SL, and drives an output node ND in accordance with an internal signal NI to produce an output signal OUT to be transmitted to another chip (not shown). A stabilizing capacitance C is connected between internal power supply line CL and internal ground line SL.
Output circuit OB is formed of a CMOS inverter formed of a p-channel MOS transistor Qa and an n-channel MOS transistor Qb.
Voltage levels of internal power supply voltages VCC1 and VSS1 produced by power supply circuits PW1 and PW2 depend on the resistance value of the terminating resistance provided at the destination chip, the on-resistances of MOS transistors Qa and Qb, output voltage VOUT of output signal OUT, and an input signal voltage VIN at the destination chip.
Reference voltage VTT is set to a voltage level of VCC/2, i.e., a half of power supply voltage VCC (VSS=0V). Now, a signal output operation of the semiconductor integrated circuit device shown in FIG. 65 will be described below with reference to a signal waveform diagram of FIG. 66.
Power supply circuit PW1 supplies internal power supply voltage VCC1 lower than power supply voltage VCC. Power supply circuit PW2 supplies another internal power supply voltage VSS1 higher than ground voltage VSS. The internal circuit operates using both power supply voltage VCC and ground voltage VSS as the operation power supply voltages, and internal signal NI changes between power supply voltage VCC and ground voltage VSS.
When internal signal NI is at L-level, output circuit OB is in such a state that MOS transistor Qa is on while MOS transistor Qb is off, and output signal OUT is held at the voltage level determined by the terminating resistance and the on-resistance of MOS transistor Qa. When internal signal rises from L-level to H-level, MOS transistor Qa is turned off, and MOS transistor Qb is turned on. When the voltage difference between the internal signal NI and the other power supply potential VSS1 exceeds a threshold voltage of MOS transistor Qb, discharging of output node ND starts, so that the voltage level of output signal OUT lowers. Finally, output signal OUT is stabilized at the voltage level determined by the ratio between the terminating resistance and the on-resistance of MOS transistor Qb. If the terminating resistance is not present, the H-level (VOH) of output signal OUT is the voltage level of internal power supply voltage VCC1, while the L-level of output signal OUT is the voltage level of the other power supply voltage VSS1.
In the structure of the semiconductor integrated circuit device shown in FIG. 65, the values of on-resistances of MOS transistors Qa and Qb are adjusted by setting the voltage levels of internal power supply voltages VCC1 and VSS1 to appropriate values, respectively, if the terminating resistance is present.
For example, consider a differential amplifier DA at an input portion of the destination chip CHa as shown in FIG. 67. Differential amplifier DA receives input signal VIN (output signal OUT of integrated circuit device CH shown in FIG. 65) at its negative input through a terminating resistance RT, and receives input signal VIN at its positive input. The negative input of differential amplifier DA is held at reference voltage VTT. The terminating resistance RT has a resistance value which is determined in accordance with a characteristic impedance of a transmission path for transmitting output signal OUT. It is now assumed that the terminating resistance RT has the resistance value of 50 .OMEGA., the L-levels of output signal OUT and input signal VIN shown in FIG. 65 are equal to (VTT-400 mV), and the on-resistances of transistors Qa and Qb in output circuit OB shown in FIG. 65 are 25 .OMEGA.. In this case, lower potential internal power supply voltage VSS1 is set to a value of (VTT-600 mV). Likewise, internal power supply voltage VCC1 is set to (VTT+600 mV) if the H-levels of output and input signals OUT and VIN are (VTT+400 mV). In this case, the voltage levels of internal power supply voltages VCC1 and VSS1 are determined in accordance with the on-resistances of MOS transistors Qa and Qb. In other words, by changing the voltage levels of internal power supply voltages VCC1 and VSS1, the on-resistances of MOS transistors Qa and Qb are changed, and thereby the current driving capability is adjusted. In this manner, a required fan-out can be achieved.
If terminating resistance RT is not employed, DC current can be prevented from flowing from terminating resistance RT and the on-state MOS transistor included in output circuit OB to reference voltage VTT supply (in destination chip CHa). Even in this case, internal power supply voltages VCC1 and VSS1 determine the voltage level of output signal OUT, so that the small amplitude operation can be achieved.
FIG. 68 shows a structure of power supply circuit PW1 shown in FIG. 65. In FIG. 68, power supply circuit PW1 includes resistance elements Ra and Rb of high resistances which are connected in series between power supply line VL and a node NDb, an n-channel MOS transistor Qc having a gate and a drain connected to node NDb, and an n-channel MOS transistor Qd having a drain connected to power supply line VL and a gate connected to a node NDa. MOS transistor Qc receives reference voltage VTT at its source. MOS transistor Qd has its source connected to internal power supply line CL, and generates internal power supply voltage VCC1 onto internal power supply line CL.
In the structure of the power supply circuit PW1 shown in FIG. 68, a minute current flows through high-resistance resistance elements Ra and Rb, so that MOS transistor Qc operates in the diode mode. Therefore, the voltage level on node NDb takes the value of (VTT+.vertline.Vth.vertline.), where Vth represents the threshold voltage of MOS transistor Qc. The voltage level on node NDa connecting resistance elements Ra and Rb is determined by the resistance ratio between resistance elements Ra and Rb. When resistance elements Ra and Rb have equal resistance value to each other, the voltage level on node NDa is given by the following representation with respect to ground voltage VSS. EQU (VCC+VTT+Vth)/2=(3/4)VCC+(Vth/2)
MOS transistor Qd at the output stage operates in a source-follower mode because its gate voltage is lower than power supply voltage VCC (Vth&lt;VTT=VCC/2). Therefore, internal voltage VCC1 on internal power supply line CL is given by the following representation: EQU VCC1=(3/4)VCC-(1/2)Vth
By setting the resistance ratio between resistance elements Ra and Rb to an appropriate value, the value of internal power supply voltage VCC1 expressed by the above representation can be adjusted. In this case, internal power supply voltage VCC1 changes in accordance with the voltage level of power supply voltage VCC. Power supply circuit PW2 has a structure similar to that of the power supply circuit shown in FIG. 68, and can be implemented by changing the voltage polarities and the conductivity types of the transistors. In this case, lower potential internal power supply voltage VSS1 is given by the following representation: EQU VTT/2+Vthp/2=VCC/4+Vthp/2
The Vthp represents an absolute value of the threshold voltage of the p-channel MOS transistor. If threshold voltages Vth and Vthp are equal to each other, a signal has upper and lower amplitudes each equal to (VCC/4-Vth/2) at opposite sides with respect to a center defined by reference voltage VTT (=VCC/2).
In the structure of the power supply circuit shown in FIG. 68, however, a current flows from power supply line VL through resistance elements Ra and Rb as well as MOS transistor Qc, and the voltage level of reference voltage VTT changes, so that the internal power supply voltages VCC1 and VSS1 cannot be accurately set to the intended voltage levels. The high and low levels of the signal have different amplitudes with respect to the center, and therefore symmetry in signal amplitude cannot be achieved, so that the timings at which the H- and L-levels of input signal are defined are different from each other. Accordingly, it is necessary to determine the input signal definition timing taking the worst case into account, so that a fast operation cannot be ensured.
Since the output circuit transmits signals to a large number of semiconductor integrated circuit devices, a large current flows. In this case, it is necessary to compensate for the consumed current by the stabilizing capacitance C shown in FIG. 65. If the fan-out is large, however, the stabilizing capacitance must have a large capacitance in order to compensate for the large consumed current. It is difficult to implement such a stabilizing capacitance within a restricted region on the semiconductor integrated circuit device, resulting in a disadvantage that the internal power supply voltage cannot be produced stably.
In the structure of the above prior art, the intermediate voltage VTT between the power supply voltage VCC and ground voltage VSS is produced within the semiconductor integrated circuit device, and is set to the voltage level (VCC/2) equal to a half of power supply voltage VCC. When variation in internal power supply voltage occurs in the semiconductor integrated circuit devices (semiconductor chips), the reference voltage level in each semiconductor integrated circuit device (semiconductor chip) differs from those in the other devices. Therefore, signal transmission between the semiconductor integrated circuit devices cannot be performed accurately because the reference voltage levels of the devices are different from each other.
In recent years, a system LSI in which a processor or a logic is integrated with a memory on a common semiconductor chip has been developed. In this system LSI, a data bus of a sufficiently large width can be arranged between the memory and the processor or logic (which will be referred to as a processing circuit), because these are arranged on the same semiconductor chip and there is no restriction by the number of pin terminals. This allows fast transmission of data between the processing circuit and the memory. Upon driving of the bus of such a large bit width, many circuits which drive the internal data bus operate simultaneously so that a current consumption increases to lower a power supply voltage, resulting in a reduced operation margin with respect to the power supply voltage. This is true also for the ground voltage. In the system LSI, internal data is usually transferred in synchronization with a clock signal. Therefore, a charge/discharge frequency of the internal data bus is high, and EMI (Electromagnetic Interference) caused by the semiconductor chip increases due to such fast charging and discharging so that electronic equipments near the chip may malfunction.
The foregoing large current consumption results in a large heat emission so that reliability of the system LSI decreases (because the heating may cause malfunction and/or open-circuit of internal interconnection lines).